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INTEGRATED CIRCUITS
DATA SHEET
OM6208 65 x 96 pixels matrix grey-scale LCD driver
Product specification Supersedes data of 2003 Jan 30 2003 feb 10
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 8 8.1 8.1.1 8.1.2 8.1.3 9 9.1 9.1.1 9.1.2 9.2 9.2.1 9.2.2 9.2.3 10 10.1 10.1.1 10.1.2 10.1.3 10.1.4 10.2 10.3 10.4 11 11.1 11.2 11.3 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION I/O buffers and interfaces Oscillator Address counter Display data RAM Display address counter Timing generator Data processing High voltage generator Bias voltage generator Command decoder Orthogonal function generator Reset Row drivers and column drivers RAM ADDRESSING Display data RAM structure Horizontal/vertical addressing Mirror Y Mirror X SERIAL INTERFACING Serial peripheral interface Write mode Read mode Serial interface (3-line) Write mode Read mode Read data format I2C-BUS INTERFACE Characteristics of the I2C-bus (Hs-mode) System configuration Bit transfer Start and stop conditions Acknowledge I2C-bus Hs-mode protocol Command decoder Read mode INSTRUCTIONS Description of command bits Frame frequency setting and oscillator tuning Initialization 2 11.4 11.5 11.6 11.6.1 11.6.2 11.7 11.8 11.9 11.10 11.10.1 11.10.2 11.10.3 11.11 11.12 12 13 14 15 16 16.1 16.2 16.3 17 17.1 17.2 17.2.1 17.2.2 17.3 17.4 17.4.1 17.5 17.5.1 17.5.2 17.6 17.7 17.8 18 19 20 21 22 23 24
OM6208
Reset function Power-down mode Display Control Horizontal mirroring Vertical mirroring Set Y address of RAM Set X address of RAM Bias levels LCD drive voltage LCD drive voltage generation Temperature measurement Temperature compensation Grey-scale mode and black-and-white mode N-line inversion and frame inversion LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS APPLICATION INFORMATION Protection from light Chip-on-glass displays Application examples MODULE MAKER PROGRAMMING VLCD calibration Factory defaults Configuration derived from OTP cells Defaults from interface registers Seal bit OTP architecture OTP operational effects Interface commands CALMM instruction Refresh instruction Example of filling the shift register Programming flow Programming specification DEVICE PROTECTION DIAGRAM BONDING PAD INFORMATION TRAY INFORMATION DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
2003 feb 10
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
1 FEATURES
OM6208
* Single chip LCD Multiple Row Addressing (MRA) grey-scale/colour controller/driver * Four grey levels/colours * 65 row outputs and 96 column outputs * Display Data RAM (DDRAM) 65 x 96 x 2 bits * Selectable interface: - 6.5 MHz 3-line or 4-line Serial Peripheral Interface (SPI) - 6.5 MHz 3-line serial interface - High speed I2C-bus interface. * On-chip: - Configurable voltage multiplier generating VLCD; external VLCD also possible - Four-segment VLCD temperature compensation - Generation of intermediate LCD bias voltage - Oscillator requires no external components; external clock input also possible - Integrated charge pump capacitors (reducing total system cost). * External reset input * Temperature read-back * Selectable N-line inversion and frame inversion * CMOS compatible inputs * Logic supply voltage range 1.7 to 3.3 V * High-voltage generator supply voltage range 2.4 to 4.5 V * Display supply voltage range 5 to 9 V * Low power consumption; suitable for battery operated systems 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME OM6208MU/2DA/1 - DESCRIPTION chip with bumps in tray VERSION - * Programmable row pad mirroring for compatibility with Tape Carrier Packages (TCP) and with Chip-On Glass (COG) applications * Status read which allows chip recognition * Start address line; for example, for scrolling the displayed image * Slim chip layout; suitable for COG, COF and TCP applications * Operating temperature range -40 to +85 C. 2 APPLICATIONS
* Telecom equipment * Portable instruments * Point of sale terminals. 3 GENERAL DESCRIPTION
The OM6208 is a low power CMOS LCD controller driver, designed to drive a graphic display of 65 rows and 96 columns. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD supply and bias voltages, resulting in a minimum of external components and low power consumption. The OM6208 can be interfaced to microcontrollers via a serial bus and I2C-bus. The OM6208 is manufactured in n-well CMOS technology. Operation is with the substrate at VSS potential.
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
5 BLOCK DIAGRAM
OM6208
handbook, full pagewidth
C0 to C95
R0 to R64
VDD1 VDD2 VDD3 VLCDIN BIAS VOLTAGE GENERATOR
COLUMN DRIVERS
ROW DRIVERS
DATA PROCESSING VSS1 VSS2 VOTPPROG VLCDSENSE VLCDOUT HIGH VOLTAGE GENERATOR DISPLAY DATA RAM (DDRAM) [65 x 96] x 2
ORTHOGONAL FUNCTION GENERATOR
RESET
RES
OSCILLATOR
OSC
TIMING GENERATOR T1 T2 T3 T4 T5 T6 T7 T8 I/O BUFFERS and INTERFACES COMMAND DECODER ADDRESS COUNTER DISPLAY ADDRESS COUNTER V2H V1H VC V1L V2L
MGW821
OM6208
PS [1:0]
SDATA
SCLK
MX
ID3/SA0; ID4/SA1
SDO
D/C
SDAH
Fig.1 Block diagram.
2003 feb 10
SCLH/SCE
4
SDAHOUT
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
6 PINNING SYMBOL VLCDIN VLCDOUT VLCDSENSE VDD2 VDD3 OSC D/C PS[1:0] VDD1 SDAHOUT SCLK SDAH SDO SDATA VSS2 VSS1 MX T3 T4 T1 T2 T5 T6 ID3/SA0; ID4/SA1 VDD1 SCLH/SCE VOTPPROG RES R32 to R64 VC T8 T7 V1L C95 to C48 C47 to C0 R31 to R0 V1H V2L V2H 2003 feb 10 PAD(1) 5 to 8 9 to 15 16 17 to 26 27 to 29 30 31 32 and 33 34 to 39 44 46 52 53 54 55 to 61 62 to 67 68 69 70 71 72 73 74 75 and 76 77 83 84 to 86 88 105 to 137 138 141 142 143 144 to 191 194 to 241 247 to 278 244 245 246 5 LCD row driver outputs bias buffer outputs; note 14 bias buffer output; note 14 LCD column driver outputs DESCRIPTION LCD supply voltage input; note 2 LCD supply voltage output from high voltage generator; note 2 regulation input to high voltage generator; note 2 supply voltage 2; note 3 supply voltage 3; note 3 oscillator input; note 4 data/command input/output; note 5 interface selection inputs supply voltage 1; note 3 I2C-bus data output; note 6
OM6208
serial data clock input; used in 3-line or 4-line SPI or 3-line serial interface mode I2C-bus data input; note 7 serial data output; note 8 serial data input; note 9 ground 2 (analog ground); note 10 ground 1 (digital ground); note 10 horizontal mirroring input test outputs; note 11
manufacturer device identification/I2C-bus slave address input pads; note 12 supply voltage 1 (tie-off pad) I2C-bus clock input/serial chip enable input in 3-line or 4-line SPI mode; note 5 supply voltage input for OTP programming; note 13 external reset input; active low; must be applied to initialize the chip properly LCD row driver outputs bias buffer output; note 14 test outputs; note 11
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
Notes
OM6208
1. Dummy pads are located at positions 1, 2, 4, 40 to 43, 45, 47 to 51, 78 to 82, 87, 89 to 92, 95 to 104, 139, 140, 192, 193, 242, 243, 279 and 280; alignment marks are located at positions 3 and 93; an alignment bump is located at position 94. 2. Positive power supply for the liquid crystal display (see also Figs 38, 39 and 40): a) If the internal voltage generator is used, pads VLCDIN, VLCDSENSE and VLCDOUT must be connected together. b) An external LCD supply voltage can be incorporated using the VLCDIN pad; the internal voltage generator must then switched off, pad VLCDOUT must be open-circuit (not connected to pad VLCDIN) and pad VLCDSENSE connected to the VLCDIN input; VDD2,3 should be applied according to the specified voltage range. In Power-down mode, the external LCD supply voltage must be switched off. 3. VDD2 and VDD3 supply the internal voltage generator, both have the same voltage and may be connected together outside of the chip; VDD1 supplies the remainder of the chip. VDD1, VDD2 and VDD3 can be connected together but then care must be taken with respect to the supply voltage range. 4. When the on-chip oscillator is used, the OSC input must be connected to VDD1. If an external clock signal is used, then this is connected to the OSC input. If both the oscillator and external clock are inhibited by connecting pad OSC to VSS1, the display is not clocked and may be in a DC state. To avoid this, the chip should always be put into Power-down mode before stopping the clock. 5. This input is not used with the 3-line serial interface and must be connected to VDD1 or VSS1 when this interface is in use. 6. SDAHOUT is the serial data acknowledge output from the I2C-bus interface. By connecting SDAHOUT to SDAH externally, the SDAH line becomes fully I2C-bus compatible. Having the acknowledge output separated from the serial data line is advantageous in COG applications because here the track resistance from the SDAHOUT pad to the system SDAH line can be significant and a potential divider can be generated by the bus pull-up resistor and the ITO track resistance. It is possible that during the acknowledge cycle the OM6208 will not be able to create a valid logic 0. By splitting the SDAH input from the SDAHOUT output the device could be used in a mode that ignores the acknowledge bit. Therefore in COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDAHOUT pad to the system SDAH line to guarantee a valid logic 0. When SDAHOUT is not used, it must be connected to VDD1 or VSS1. 7. When I2C-bus is not used, this pad must be connected to VDD1 or VSS1. 8. SDO is a push-pull output; when it is intended to use the readback function of the OM6208, this pad must be connected to the SDATA pad, or used separately; when I2C-bus interface is selected, this pad should be connected to VDD1 or VSS1. 9. When I2C-bus interface is selected this pin should be connected to VDD1 or VSS1. 10. Supply rails VSS1 and VSS2 must be connected together. 11. Test pads T1 to T8 are not accessible to users: T1, T2, T5 and T6 must be connected to VSS; T3, T4, T7 and T8 must be open-circuit. 12. Module identification bits: these bits may be read back via the `read back' instruction; when the I2C-bus interface is being used, these bits are the two LSBs of the slave address. 13. VOTPROG can be connected to SCLH/SCE pad to reduce the external connections. If not connected in this configuration, then VOTPROG should be open-circuit during normal operation. 14. These pads are not accessible to users and must be left open-circuit; an explanation of the bias buffer function is given in Section 11.9.
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
7 7.1 FUNCTIONAL DESCRIPTION I/O buffers and interfaces 7.6 Timing generator
OM6208
One of four industrial standard interfaces can be selected using the interface configuration inputs PS1 and PS0. Table 1 PS1 0 0 1 1 7.2 Serial/I2C-bus interface selection PS0 0 1 0 1 Oscillator SELECTED INTERFACE 3-line SPI 4-line SPI I2C-bus interface 3-line serial interface
The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not affected by operations on the data bus. 7.7 Data processing
The data processing block receives data from the RAM and the orthogonal function from the logic circuits, then selects the correct voltage level to be provided to the columns. 7.8 High voltage generator
The high voltage generator provides the programmed VLCD to the bias voltage generator block. 7.9 Bias voltage generator
The on-chip oscillator provides the clock signal for the display system. No external components are required when the internal oscillator is used. An external clock signal, if used, is connected to this input. 7.3 Address counter
The bias voltage generator generates all the voltage levels required for the MRA driving system. 7.10 Command decoder
The Address Counter (AC) assigns addresses to the display data RAM for writing. The X address X[6:0] and the Y address Y[4:0] are set separately. 7.4 Display data RAM
The command decoder identifies command words arriving at the interface and routes the data bytes that follow to their destination. 7.11 Orthogonal function generator
The OM6208 contains a 65 x 96 x 2 bit static RAM which stores the display data. The display data RAM is divided into 17 banks of 96 bytes, although only two bits of the 17th bank are used. During RAM access, data is transferred to the RAM via the serial interface. There is a direct correspondence between X address and column output number. 7.5 Display address counter
The orthogonal function generator generates a set of orthogonal functions suitable for the selected value of p (number of active rows). 7.12 Reset
The reset block handles the hardware reset input (RES) and software reset and provides all internal blocks with the required reset signal. 7.13 Row drivers and column drivers
The display is generated by simultaneously reading out the RAM content for two or four rows, depending on the current display size that is selected. This content will be processed with the corresponding set of two or four orthogonal functions and so generate the signals for switching the pixels of the display on or off according to the RAM content. The display status (all dots on/all dots off and normal/inverse video) is set by the bits DON, DAL and E in the command Display control (see Table 8).
The OM6208 contains 65 row and 96 column drivers which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. A typical MRA driving scheme with waveforms for p = 4 is shown in Fig.2. The value of p represents the number of simultaneously selected rows.
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
handbook, full pagewidth
G1(t)
G2(t)
G3(t)
F1(t)
F2(t)
F3(t)
F4(t)
Vcol(max) G1(t) VC Vcol(min) G1(t) = C [+ F1(t) - F2(t) - F3(t) + F4(t) ]
G1(t)
G2(t)
G3(t)
F1(t)
F2(t)
F3(t)
F4(t)
Vcol(max) G1(t) VC Vcol(min) G1(t) = C [- F1(t) - F2(t) - F3(t) + F4(t) ]
MGW822
Fig.2 Typical MRA LCD driver waveforms for p = 4.
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
8 RAM ADDRESSING
OM6208
Data is downloaded in bytes into the RAM matrix of the OM6208 as indicated in Fig.3. The display RAM has a matrix of 65 x 96 x 2 bits. The columns are addressed by the address pointer. The address ranges (decimal values)
are X = 0 to 95 and Y = 0 to 16. The Y address represents the bank number. Addresses outside these ranges are not allowed. The Data Order Bit (DOR) defines the bit order (LSB on top or MSB on top) for writing into the RAM.
handbook, full pagewidth DOR
=1
P0 P1 P2 P3 P0 P1 P2 P3
LSB MSB
bank 0 top of LCD R0 bank 1 R4 bank 2 R8 bank 3 R12
LSB
P0 DB0 MSB DB1 DB2 P0 LSB P1 MSB
DB3 P1 LSB DB4 P2 MSB DB5 P2 LSB DB6 P3 MSB
MSB DB7 P3 LSB
DOR = 0 LSB DB0 LSB
DB1 DB2 P3 MSB P2 LSB P3
. . .
. . .
bank 13
. .
R16
LCD
R52
DB3 P2 MSB DB4 P1 LSB DB5 P1 MSB DB6 P0 LSB
bank 14 R56 bank 15 R60
X X X X X X
MSB DB7 P0 MSB
bank 16 R64
MGW823
Fig.3 DDRAM-to-display mapping.
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
8.1 Display data RAM structure
OM6208
The mode for storing data in the display data RAM is dependent on: * Horizontal/vertical addressing mode set by bit V in the `RAM addressing mode' instruction * Data order set by bit DOR in the `data order' instruction * Mirror the X-axis set by input MX. 8.1.1 HORIZONTAL/VERTICAL ADDRESSING
In the horizontal addressing mode (V = 0) the X address increments after each byte. After the last X address (X = 95), X wraps around to 0 and Y increments to address the next row (see Fig.4). In the vertical addressing mode (V = 1), the Y address increments after each byte. After the last Y address (Y = 16), Y wraps around to 0 and X increments to address the next column (see Fig.5). After the very last address, the address pointers wrap around to address X = 0 and Y = 0 in both horizontal and vertical addressing modes.
Two different addressing modes are possible; horizontal addressing mode and vertical addressing mode.
handbook, full pagewidth
0 96 192 288 384
1 97 193 289 385
2 98 194 290 386
95 191
0
Y address
1440 1536 0
1441 1537
1442
1535 1631 X address 95 16
MGW824
Fig.4 Sequence of writing data bytes into RAM with horizontal addressing (V = 0).
handbook, full pagewidth
0 1 2 3 4 5
17 18 19 20 21 22
0
Y address
16 0
33 X address
1631 95
16
MGW825
Fig.5 Sequence of writing data bytes into the RAM with vertical addressing (V = 1).
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
8.1.2 MIRROR Y
OM6208
The Mirror Y (MY) bit allows vertical mirroring: * When MY = 1, the Y address space is mirrored; the address Y = 0 is then located at the bottom of the display (see Fig.6)
* When MY = 0, the mirroring is disabled and the address Y = 0 is located at top of the display (see Fig.7). Refer also to Section 11.6.
handbook, full pagewidth
16
0
0
X address Y address
95
MGW826
Fig.6 RAM format addressing (MY = 1).
handbook, full pagewidth
0
16
0
X address Y address
95
MGW827
Fig.7 RAM format addressing (MY = 0).
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
8.1.3 MIRROR X
OM6208
The Mirror X (MX) input allows a horizontal mirroring: * When MX = 1, the X address space is mirrored; the address X = 0 is then located at the right side (Xmax) of the display (see Fig.8)
* When MX = 0, the mirroring is disabled and the address X = 0 is located at the left side (column 0) of the display (see Fig.9). Refer also to Section 11.6.
handbook, full pagewidth
0
16
95
X address Y address
0
MGW828
Fig.8 RAM format addressing (MX = 1).
handbook, full pagewidth
0
16
0
X address Y address
95
MGW829
Fig.9 RAM format addressing (MX = 0).
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
9 SERIAL INTERFACING 9.1.1 WRITE MODE
OM6208
Communication with the microcontroller can occur via a clock-synchronized serial peripheral interface. It is possible to select two different 3-line (SPI and serial interface) or a 4-line SPI interface. Selection is done via the PS[1:0] inputs. 9.1 Serial peripheral interface
The Serial Peripheral Interface (SPI) is a 3-line or 4-line interface for communication between the microcontroller and the LCD driver chip. Three lines are common to both 3-line and 4-line SPI, these are SCE (chip enable), SCLK (serial clock) and SDATA (serial data). For the 4-line SPI a separate D/C line is added. The OM6208 is connected to the serial data I/O of the microcontroller by pads SDATA (data input) and SDO (data output) connected together.
The display data/command indication may be controlled by software or by the D/C select pin. When the D/C pad is used, display data is transmitted when D/C is HIGH, and command data is transmitted when D/C is LOW (see Figs 10 and 11). When D/C is not used, the `display data length' instruction is used to indicate that a specific number of display data bytes (1 to 255) are to be transmitted (see Fig.11). The next byte after the display data string is handled as an instruction command. When the 3-line SPI interface is used the display data/command is controlled by software (see Fig.12). If SCE is pulled high during a serial display data stream, the interrupted byte is invalid data but all previously transmitted data is valid. The next byte received will be handled as an instruction command (see Fig.13).
handbook, full pagewidth
SCE
D/C
SCLK
SDATA
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
MGW744
Fig.10 4-line SPI bus protocol; transmission of one byte.
handbook, full pagewidth
SCE
D/C
SCLK
SDATA
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5
MGW745
Fig.11 4-line SPI bus protocol; transmission of several bytes.
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
handbook, full pagewidth
SCE
SCLK
SDATA
DB7 DB6 DB5 DB4
DB2 DB1 DB0 data
data
last data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 instruction
display length instruction and length data (two bytes)
display data string
MGW746
Fig.12 3-line SPI bus protocol; transmission of several bytes.
handbook, full pagewidth
SCE
SCLK
SDATA
data
data
data
data
data
data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4
MGW747
display data string
instruction
Fig.13 3-line SPI bus protocol: transmission interrupted by SCE.
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
9.1.2 READ MODE
OM6208
The read mode of the interface means that the microcontroller reads data from the OM6208. To do so the microcontroller first has to send a command, the read status command, and then OM6208 will respond by transmitting data on the SDO line. After that, SCE is required to go HIGH (see Fig.14). The OM6208 samples the SDATA data at rising SCLK edges, but shifts SDO data at falling SCLK edges. Thus
the SDO data is available to be read by the microcontroller at rising SCLK edges. After the read status command has been sent, the SDATA line must be set to 3-state (high-impedance) not later than at the falling SCLK edge of the last bit (see Fig.14). For the read data format, see Section 9.2.3; the serial interface timing diagram is given in Chapter 15.
handbook, full pagewidth
SCE
RES
SCLK
SDATA
DB7 DB6 DB5 DB4 DB3 DB2
DB1 DB0
SDO instruction
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 read out data
MGU629
Fig.14 Read mode SPI 3- and 4-line interfaces.
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
9.2 Serial interface (3-line)
OM6208
The serial interface is also a 3-line bidirectional interface for communication between the microcontroller and the LCD driver chip. The three lines are SCE (chip enable), SCLK (serial clock) and SDATA (serial data). The OM6208 is connected to the SDA of the microcontroller by the SDATA (data input) and SDO (data output) pads which are connected together. 9.2.1 WRITE MODE
pulses have no effect and no power is consumed by the serial interface. A falling edge on SCE enables the serial interface and indicates the start of data transmission. Figures 16, 17 and 18 show the protocol of the write mode: * When SCE is HIGH, SCLK clocks are ignored. During the HIGH time of SCE the serial interface is initialized (see Fig.16) * At the falling SCE edge, SCLK must be LOW (see Fig.32) * SDATA is sampled at the rising edge of SCLK * D/C indicates whether the byte is a command (D/C = 0) or RAM data (D/C = 1) byte; it is sampled with the first rising SCLK edge * If SCE stays LOW after the last bit of a command/data byte, the serial interface is ready for the D/C bit of the next byte at the next rising edge of SCLK (see Fig.17) * A reset pulse with RES interrupts the transmission. The data being written into the RAM may be corrupted. The registers are cleared. If SCE is LOW after the rising edge of RES, the serial interface is ready to receive the D/C bit of a command/data byte (see Fig.18).
The write mode of the interface means that the microcontroller writes instructions and data to the OM6208. Each data packet contains a control bit D/C and a transmission byte. If D/C is LOW, the following byte is interpreted as command byte. The instruction set is given in Table 7. If D/C is HIGH, the following byte is stored in the display data RAM. After every data byte the address counter is incremented automatically. The general format of the write mode and the definition of the transmission byte is shown in Fig.15. Any instruction can be sent in any order to the OM6208. The MSB is transmitted first. The serial interface is initialized when SCE is HIGH. In this state, SCLK clock
handbook, full pagewidth
transmission byte (1)
D/C
D7 MSB
D6
D5
D4
D3
D2
D1
D0 LSB
D/C
transmission byte
D/C
transmission byte
D/C
transmission byte
MGW713
(1) A transmission byte may be a command byte or a data byte.
Fig.15 Serial data stream, write mode.
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
handbook, full pagewidth
SCE
SCLK
SDATA
D/C
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
MGU630
Fig.16 Write mode: a control bit followed by a transmission byte.
handbook, full pagewidth
SCE
SCLK
SDATA
D/C
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C transmission byte
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C transmission byte
MGU631
Fig.17 Write mode: transmission of several bytes.
handbook, full pagewidth
SCE
RES
SCLK
SDATA
D/C DB7 DB6 DB5 DB4
D/C
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D/C
DB7 DB6
MGU632
Fig.18 Write mode: interrupted by reset (RES).
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
9.2.2 READ MODE
OM6208
handbook, full pagewidth
SCE
SCLK
SDATA
D/C
DB7 DB6 DB5 DB4
DB3 DB2 DB1 DB0
D/C
SDO
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
MCE176
Fig.19 Read mode serial interface 3-line.
The read mode of the interface means that the microcontroller reads data from the OM6208. To do so the microcontroller first has to send a command, the read status command, and then the following byte is transmitted in the opposite direction using SDO (see Fig.19). After that, SCE is required to go HIGH before a new command is sent. The OM6208 samples the SDATA data at rising SCLK edges and shifts SDO data at falling SCLK edges. Thus the SDO data is available for the microcontroller to read at rising SCLK edges. After the read status command has been sent, the SDATA line must be set to 3-state not later then at the falling SCLK edge of the last bit (see Fig.19).
The 8th read bit is shorter than the others because it is terminated by the rising SCLK edge (see Fig.35). The last rising SCLK edge sets SDO to 3-state after the delay time t4. 9.2.3 READ DATA FORMAT
Regardless of which serial interface is used there are five bits that can be read (ID1 to ID4 and VM) and one temperature register. For the bits, one bit is transmitted per byte read and is selected by issuing the appropriate read instruction from the instruction set. Bits ID1 and ID2 are hard-wired so that ID1 always returns a logic 0 and ID2 always returns a logic 1. Bits ID3 and ID4 are the identification bits and are set via ID3/SA0 and ID4/SA1 pads. The format for the read bit, B, is shown in Table 2.
Table 2
Read data format D6 B D5 B D4 B D3 B D2 B D1 B D0 (LSB) B
D7 (MSB) x(1) Note 1. x = undefined.
Table 3 Read temperature sensor Sending the instruction to read back the temperature sensor data will select the following status byte. D7 (MSB) x(1) Note 1. x = undefined. D6 TD[6] D5 TD[5] D4 TD[4] D3 TD[3] D2 TD[2] D1 TD[1] D0 (LSB) TD[0]
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Product specification
65 x 96 pixels matrix grey-scale LCD driver
10 I2C-BUS INTERFACE 10.1 Characteristics of the I2C-bus (Hs-mode) 10.1.1 SYSTEM CONFIGURATION
OM6208
Definition (see Fig.20): * Transmitter: the device that sends the data to the bus * Receiver: the device that receives the data from the bus * Master: the device that initiates a transfer, generates clock signals and terminates a transfer * Slave: the device addressed by a master * Multi-master: more than one master can attempt to control the bus at the same time without corrupting the message * Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted * Synchronisation: procedure to synchronize the clock signals of two or more devices.
The I2C-bus Hs-mode is for bidirectional, two-line communication between different ICs or modules with speeds up to 3.4 MHz. The only difference between Hs-mode slave devices and F/S-mode slave devices is the speed at which they operate, therefore the buffers on the SDAH output have an open drain. This is the same for I2C-bus master devices which have an open-drain SDAH output and a combination of an open-drain pull-down and current source pull-up circuits on the SCLH output. Only the current source of one master is enabled at any one time and only during Hs-mode. Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy.
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
MGA807
Fig.20 System configuration.
10.1.2
BIT TRANSFER
One data bit is transferred during each clock pulse (see Fig.21). The data on the SDAH line must remain stable
during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal.
handbook, full pagewidth
SDA
SCL data line stable; data valid change of data allowed
MBC621
Fig.21 Bit transfer.
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Product specification
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10.1.3 START AND STOP CONDITIONS
OM6208
Both data and clock lines remain HIGH when the bus is not busy (see Fig.22). A HIGH-to-LOW transition of the data
line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P).
handbook, full pagewidth
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.22 Definition of START and STOP conditions.
10.1.4
ACKNOWLEDGE
Each byte of 8 bits is followed by an acknowledge bit (see Fig.23). The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the
slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
handbook, full pagewidth
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement
MBC602
1
2
8
9
Fig.23 Acknowledge on the I2C-bus.
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Product specification
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10.2 I2C-bus Hs-mode protocol
OM6208
The OM6208 is a slave receiver/transmitter. If data is to be read from the device the SDAHOUT and SDAH pads must be connected for acknowledge to be used (see Table 1, note 6). Hs-mode can only commence after the following conditions. * START condition (S) * 8-bit master code (00001XXX) * not-acknowledge bit (A). The master code has two functions as shown in Figs 24 and 25, it allows arbitration and synchronization between competing masters at F/S-mode speeds, resulting in one winner. Also the master code indicates the beginning of an Hs-mode transfer. As no device is allowed to acknowledge the master code, then a master code transmission must be followed by a not-acknowledge (A). After this A bit, and the SCLH line has been pulled up to a HIGH level, the active master switches to Hs-mode and enables at tH the current-source pull-up circuit for the SCLH signal (see Fig.25). The active master will then send a repeated START condition (Sr) followed by a 7-bit slave address with a Table 4 Co 0 1 - - Co and Sr definition D/C - - 0 1 R/W - - 0 1 0 1
R/W bit, and receives an acknowledge bit (A) from the selected slave. After each acknowledge bit (A) or not-acknowledge bit (A) the active master disables its current-source pull-up circuit. The active master re-enables its current source again when all devices have released and the SCLH signal reaches a HIGH level. The rising of the SCLH is done by a resistor pull-up and so is slower, the last part of the SCLH rise time is speeded up because the current source is enabled. Data transfer only switches back to F/S-mode after a STOP (P) condition. The write sequence that occurs after the Hs-mode is selected is shown in Fig.26. The sequence is initiated with a START (S) condition from the I2C-bus master which is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I2C-bus transfer. After an acknowledgement cycle of a write (W), one or more command words follow which define the status of the addressed slaves. A command word consists of a control byte, which defines Co and D/C, plus a data byte (see Fig.26 and Table 4). The last control byte is tagged with a cleared most significant bit, the continuation bit Co. The control and data bytes are also acknowledged by all addressed slaves on the bus.
ACTION last control byte to be sent; only a stream of data bytes are allowed to follow; this stream may only be terminated by a STOP or repeated START condition another control byte will follow the data byte unless a STOP or repeated START condition is received data byte will be decoded and used to set up the device data byte will return the status byte data byte will be stored in the display RAM RAM read back is not supported transmission the I2C-bus master issues a STOP condition (P) and switches back to F/S-mode, however, to reduce the overhead of the master code, it i s possible that a master links a number of Hs-mode transfers, separated by repeated START conditions (Sr). A read sequence (see Fig.27) follows after the Hs-mode is selected. The OM6208 will immediately start to output the requested data until a not acknowledge is transmitted by the master. The write access should be terminated by a repeated START condition so that the Hs-mode is not disabled. 21
After the last control byte, depending on the D/C bit setting, a series of display data bytes or command data bytes may follow. If the Sr bit was set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is automatically updated and the data is directed to the intended OM6208 device. If the Sr bit of the last control byte was set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. The acknowledgement after each byte is made only by the addressed OM6208. At the end of the 2003 feb 10
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Product specification
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OM6208
handbook, full pagewidth
,,,,,,,,,, ,,,,,,,,,,
F/S-mode S MASTER CODE A Sr SLAVE ADD. R/W A
Hs-mode (current-source for SCLH enabled)
DATA (n bytes + ack.)
,, ,, ,,,, ,,,,
F/S-mode A/A P Hs-mode continues Sr SLAVE ADD.
MSC616
Fig.24 Data transfer format in Hs-mode.
handbook, full pagewidth
S
8-bit Master code 00001xxx
A
t1 tH
SDAH
SCLH
1
2 to 5
6
7
8
9
F/S mode
Sr
7-bit SLA
R/W
A
n x (8-bit DATA
+
A/A)
Sr P
SDAH
SCLH
1
2 to 5
6
7
8
9
1 Hs-mode
2 to 5
6
7
8
9 If P then F/S mode If Sr (dotted lines) then Hs-mode
tH = MCS current source pull-up = Rp resistor pull-up
tFS
MSC618
Fig.25 Complete data transfer in Hs-mode.
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Product specification
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OM6208
handbook, full pagewidth
acknowledge from OM6208
acknowledge from OM6208
acknowledge from OM6208
acknowledge from OM6208
acknowledge from OM6208
SS Sr 0 1 1 1 1 A A 0 A 1 D/C 10 slave address
control byte
A
data byte
A 0 D/C
control byte
A
data byte n 0 bytes MSB . . . . . . . . . . . LSB
AP
R/W Co
2n 0 bytes
Co
1 byte
MGW830
Fig.26 Master transmits in Hs-mode to slave receiver; write mode.
handbook, full pagewidth
acknowledgement from OM6208 SS Sr 0 1 1 1 1 A A 1 A 10 slave address R/W
(1)
NOT acknowledgement from Master
status information
AP
STOP condition
MGW831
(1) These bits are set by inputs ID3/SA0 and ID4/SA1.
Fig.27 Master receives from slave transmitter (status register is read); read mode.
10.3
Command decoder
The command decoder identifies command words that arrive on the I2C-bus: * Pairs of bytes - first byte determines whether information is display or instruction data - 2nd byte contains information. * Stream of information bytes after Co = 0; display or instruction data depending on last D/C.
The most-significant bit of a control byte is the continuation bit Co. If this bit is logic 1, it indicates that only one byte, either command or RAM-data, will follow. If this bit is logic 0, it indicates that a series of bytes, either command or RAM-data, may follow. The DB6 bit of a control byte is the RAM-data/command bit D/C. When this bit is logic 1, it indicates that a RAM-data byte will be transferred next. If the bit is logic 0, it indicates that a command byte will be transferred next.
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10.4 Read mode
OM6208
I2C-bus
read mode operates differently from the other interfaces. Two different status bytes can be read back and are selected by first sending a `read' instruction. A repeated START or STOP and START must then be generated followed by the slave address with the R/W bit set to read in order to read the status register. Table 5 Read status byte ID1, ID2 and VM D6 x(1) D5 x(1) D4 x(1)
Sending the instruction to read ID1, ID2 and VM will select the status byte shown in Table 5. Sending the instruction to read back the temperature sensor will select the status byte shown in Table 6.
D7 (MSB) x(1) Notes 1. x = undefined.
D3 x(1)
D2 VM
D1 ID2(2)
D0 (LSB) ID1(2)
2. Bits ID3 and ID4 are not available for I2C-bus because they are used to make up the two LSBs of the slave address. Table 6 Read temperature sensor D6 TD[6] D5 TD[5] D4 TD[4] D3 TD[3] D2 TD[2] D1 TD[1] D0 (LSB) TD[0]
D7 (MSB) x(1) Note 1. x = undefined.
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11 INSTRUCTIONS The OM6208 may be interfaced via 3-line or 4-line Serial Peripheral Interface (SPI), 3-line serial interface or I2C-bus interface. In all cases, processing of instructions is asynchronous and does not require the internal/external oscillator to be running. Data transmission to OM6208 may be of two types, those that define the operating mode of the device (commands) and those that fill display RAM (data). Table 7 lists all commands that are recognised by OM6208. The Most Significant Bit (MSB) is sent first. The mode in which the D/C bit is defined varies with the type of serial interface that is used. Table 7 Instruction set D/C bit definitions:
OM6208
* With 4-line SPI interface selected, the D/C bit is implemented as hard-wired input at pad D/C * With 3-line SPI interface selected, the D/C bit is not implemented and all transmission are commands by default unless preceded by the Display data length command * With 3-line serial and I2C-bus interface selected, the D/C bit is implemented through the interface protocol. Commands can consist of one byte (single-byte) and two bytes (double-byte). Unless otherwise specified, commands may be executed in any order.
Instructions not expressly defined in this table and reserved instructions must not be used. COMMAND BYTE COMMAND NAME Write data Horizontal addressing Horizontal addressing Power control Charge pump control Set VPR Set VPR Set bias Display mode Display mode Display mode Data order RAM addressing Vertical addressing Vertical addressing Vertical mirroring ID read ID read ID read ID read Temperature sense VM read Row control D/C (MSB) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D7 0 0 0 0 (1) 0 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 D6 D6 0 0 0 0 (1) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D5 D5 0 0 1 1 (1) 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 D4 D4 0 1 0 1 (1) 0 Vpr4 1 0 0 0 0 0 1 1 0 1 1 1 1 1 1 0 D3 D3 X3 (1) 1 1 (1) 0 Vpr3 0 0 0 1 1 1 Y3 1 MY 1 1 1 1 1 1 0 D2 D2 X2 X6 PC 1 (1) Vpr7 Vpr2 BS2 1 1 1 0 0 Y2 1 (1) 0 0 1 1 1 1 0 D1 D1 X1 X5 (1) 0 S1 Vpr6 Vpr1 BS1 0 1 1 0 1 Y1 1 (1) 1 1 0 0 1 1 0 D0 (LSB) D0 X0 X4 (1) 1 S0 Vpr5 Vpr0 BS0 DAL E DON DOR V Y0 Y4 (1) 0 1 0 1 0 1 BRS write Vpr register write Vpr register set bias all on/normal display normal/inverse display display ON/OFF swap RAM MSB/LSB order vertical or horizontal mode set Y address set Y address mirror Y identification: ID1(2)(3) identification: ID2(2)(3) identification: ID3(2) identification: ID4(2) temperature read back voltage monitor(3)(4) swap the bottom rows FUNCTION DESCRIPTION RAM data set X address; lower 4 bits set X address; upper 3 bits charge pump on/off set multiplication factor
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Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
COMMAND BYTE COMMAND NAME Software reset NOP Display data length Temperature compensation Temperature compensation Frame frequency range, oscillator tune and mode Temperature compensation enable Oscillator selection OTP programming LOAD 0 LOAD 1 Select factory defaults N-line inversion and super-frame inversion D/C (MSB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Notes 1. = don't care. 2. ID1, ID2, ID3, ID4 and VM are read back via interface as described in Section 9.2.3. Reading back with I2C-bus interface is possible for temperature, ID1, ID2 and VM, as described in Section 10.4. 3. ID1 will always return to logic 0; ID2 will always return to logic 1. The VM bit is set to logic 1 when the charge pump is running and logic 0 when the charge pump is not running. 4. If the Factory Defaults bit (MMFD) has been programmed to 1, then the SFD instruction is ignored and the device will always use the OTP default data. 1 1 1 D7 0 (1) 0 (1) 0 MOD 1 0 1 1 1 1 1 FI 0 1 1 1 1 1 1 1 1 D6 1 1 1 D6 0 0 0 T2 1 0 1 1 1 1 0 NL6 1 0 0 1 1 1 1 1 1 D5 1 1 1 D5 1 1 1 T1 1 1 1 0 0 1 1 NL5 (1) 1 1 0 1 1 1 1 1 D4 0 0 0 D4 1 1 1 T0 0 1 1 1 1 0 0 NL4 (1) 0 0 1 0 0 0 1 1 D3 0 0 1 D3 1 (1) 1 (1) 1 (1) 1 1 0 1 1 1 1 NL3 (1) 0 1 0 1 0 1 0 1 D2 0 0 0 D2 0 0 1 FR2 0 0 0 0 0 1 1 NL2 (1) 0 1 (1) 0 1 1 1 (1) D1 1 1 0 D1 0 0 0 FR1 1 1 OSE 0 0 0 0 NL1 (1) (1) 0 (1) 0 (1) 1 (1) (1) D0 (LSB) 0 1 0 D0 0 SLA0 1 SLC0 0 FR0 TCE EC CAL MM 0 1 SFD 1 NL0 (1) (1) 0 (1) 1 (1) (1) (1) (1) FUNCTION DESCRIPTION internal reset no operation display data length for 3-line SPI set TC slopes A and B (SLA and SLB) set TC slopes C and D (SLC and SLD) frame frequency range and oscillator tune and working mode enable/disable temperature compensation external oscillator enter calibration mode and control programming write 0 to shift register write 1 to shift register enable/disable defaults N-line inversion and super-frame Inversion reserved reserved reserved reserved reserved reserved reserved reserved for testing reserved for testing
SLB2 SLB1 SLB0 SLD2 SLD1 SLD0
SLA2 SLA1 SLC2 SLC1
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Product specification
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11.1 Description of command bits Bit descriptions BIT DON E DAL MY PC DOR V BRS EC CALMM TCE OSE SFD MOD SLA[2:0] SLB[2:0] SLC[2:0] SLD[2:0] X[6:0] Y[4:0] S[1:0] NL[6:0] FR[2:0] T[2:0] D[7:0] VPR[7:0] BS[2:0] FI Notes display off normal display normal display no Y mirroring charge pump off normal data order horizontal addressing bottom rows are not mirrored internal oscillator is selected exit OTP calibration mode disable temperature compensation disable OTP programmed voltage use interface programmed data grey-scale mode is selected 0 display on inverse video mode all pixel on Y mirroring charge pump on MSB/LSB transposed for RAM data vertical addressing bottom rows are mirrored external clock to be used enter OTP calibration mode(1) enable temperature compensation enable OTP programmed voltage(1) use OTP programmed data(2) black-and-white mode is selected 1
OM6208
Table 8
RESET STATE 0 0 1 0 0 0 0 0 0 0 1 0 0 0 000(2) 000(2) 000(2) 000(2) 0000000 00000 0000(2) 0001101(2) 001(2)(3) 110(2)(3) 00000000 00000000(2) 000(2) 0(2)
select slope for segment A select slope for segment B select slope for segment C select slope for segment D sets X address (column) for writing in the RAM sets Y address (bank) for writing in the RAM charge pump multiplication factor (see Table 10) sets N-line inversion (see Table 18) sets frame frequency range (see Table 11) oscillator tune; sets frame frequency within a range (see Table 11) display data length for 3-line SPI interface VPR register bias setting level (see Table 13) super-frame inversion
1. Calibration mode may not be entered if the SEAL bit has been set. Programming is only possible when in calibration mode. 2. These values can be set by the module maker. If the factory defaults OTP bit (MMFD) has been set then these values cannot be changed via the interface. Otherwise, the OTP data will only be used if bit SFD is set to 1. 3. FR[2:0] = 001 and T[2:0] = 110 gives 150 Hz as default frame frequency.
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Product specification
65 x 96 pixels matrix grey-scale LCD driver
Table 9 DON 0 Display and power mode bits DON, DAL and E DAL(1) 0 E(2) X(3) DESCRIPTION display off; all row and column outputs at VSS; oscillator on; HV generator enabled Power-down mode; display off; all row and column outputs at VSS; oscillator off; HV generator disabled normal display mode inverse display mode all pixels on
OM6208
Table 11 Frame frequencies for fosc = 400 kHz FR2 0 0 0 0 1 1 1 1 FR1 0 0 1 1 0 0 1 1 FR0 0 1 0 1 0 1 0 1 DIVISION RATIO 2448 3265 4082 4896 5714 7340 8968 11428 fframe (Hz) 163.4 122.5 98.0 81.7 70.0 54.5 44.6 35.0
0
1
X(3)
1 1 1 Notes
0 0 1
0 1 X(3)
1. The DAL bit has priority over the E bit. 2. Refer also to Table 17. 3. X = don't care. Table 10 Multiplication settings for charge pump S1 0 0 1 1 11.2 S0 0 1 0 1 VOLTAGE MULTIPLIER 4x 5x 6x 7x
Oscillator tuning is controlled by the parameter T[2:0]. As a result of oscillator tuning, fOSC is increased by approximately 4% per step according to the equation f OSC = 400 kHz x ( 1 + 0.04 x T ) where T is the decimal value of T[2:0]. Example. For the default values given in Table 8 (i.e. FR[2:0] = 001 and T[2:0] = 110) the selected frame frequency is 122.5 Hz x (1 + 6 x 0.04) = 151.9 Hz. Equation (1) shows the typical value of the oscillator frequency. The accuracy of this parameter is defined in Chapter 15. The frame frequency accuracy results directly from the oscillator accuracy. 11.3 Initialization (1)
Frame frequency setting and oscillator tuning
Grey-scale mode and black-and-white mode require different frame frequencies. The appropriate frame frequency (fframe) is derived from the oscillator frequency (fosc) using a presettable divider as shown in the equation f frame f OSC = -------------------------------division ratio
Immediately following power-on, all internal registers and the RAM content are undefined. A reset pulse must be applied to the RES pad. Reset is accomplished by applying an external reset pulse (active LOW) to the RES input. When reset occurs within the specified time, all internal registers are reset, however the RAM remains undefined. The state after reset is described in Section 11.4. At power-on, the RES input must be 0.3VDD1 when VDD1 reaches VDD(min) (or higher) within the maximum time tVHRL after VDD1 going HIGH (see Fig.37). Alternatively a reset pulse can be applied when VDD1 is stable. A reset can also be made by sending a reset command. This command can be used during normal operation but not to initialize the chip after power-on. After power-off, the RES input must not be HIGH when VDD1 is not HIGH.
There are eight possible divider settings and these are selected by the parameter FR[2:0], see Table 11.
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11.4 Reset function 11.7 Set Y address of RAM
OM6208
After reset, the LCD driver is in Power-down mode, the RAM is undefined and the internal registers have the status shown in Table 8. 11.5 Power-down mode
Y[4:0] defines the Y address of the display RAM. Table 12 Y address range Y4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 11.8 Y3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 Y2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 Y1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Y0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 DISPLAY RAM bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 bank 9 bank 10 bank 11 bank 12 bank 13 bank 14 bank 15 bank 16
In the Power-down mode: * All LCD outputs (row and column outputs) are at VSS (display off) * Bias generator and VLCD generator are switched off; external VLCD supply can be applied or disconnected * Oscillator is off (an external clock is possible) * RAM contents are unchanged; RAM data can be written * VLCD is discharged to VSS. Power-down mode is active when the display is off (DON = 0) and all the pixels are on (DAL = 1). 11.6 Display Control
The bits DON, E and DAL select the display mode (see Table 9). 11.6.1 HORIZONTAL MIRRORING
When the MX input is at logic 0, the display RAM is written from left to right (X = 0 is on the left side). When the MX input is set to 1, the display RAM is written from right to left (X = 0 is on the right side). The MX input value has an impact on the way the RAM is written: if a horizontal mirroring of the display is desired, the RAM must be rewritten after changing the MX pad value. 11.6.2 VERTICAL MIRRORING
Set X address of RAM
The X address points to the columns. The range of X is 0 to 95. 11.9 Bias levels
When the MY bit is set to logic 1, the display is mirrored vertically. A change of this bit has an immediate effect on the display, it is not necessary to rewrite RAM for the effect to take place.
The OM6208 is a grey-scale driver able to provide different bias voltage levels for rows and columns. The row voltage values are VLCD, VSS and VC, generated using the resistor chain shown in Fig.28. The five levels used to drive the columns are shown in Fig.28. These are V2L, V1L, VC, V1H and V2H, all of which depend on the value of alpha. Table 13 shows all possible combinations of alpha settable by programming the BS[2:0] bits.
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
handbook, halfpage
VLCD = Vrow(max) R V2H
F G
R V1H R VC R V1L R V2L R VSS = Vrow(min)
is in the range 0.0 to 1.05.
MGW832
Fig.28 Bias system.
Table 13 Bias setting levels for p = 4 BS2 0 0 0 0 1 1 1 1 BS1 0 0 1 1 0 0 1 1 BS0 0 1 0 1 0 1 0 1 F/G 1.000 1.075 1.150 1.225 1.300 1.375 1.450 1.525 0.00 0.15 0.30 0.45 0.60 0.75 0.90 1.05 a 4.00 4.30 4.60 4.90 5.20 5.50 5.80 6.10
Because the voltage level of the row depends on the programmed bias level, it can be seen that F G The situation where F = G occurs only when BS[2:0] is zero and alpha is zero. In this case R = 0 and G = F; therefore V2H = VLCD and V2L = VSS, also two of the internal buffers are no longer needed and therefore are switched off to reduce power consumption. The relationship between F and G is defined by the parameter a (indicated in Table 13) and p as follows F a --- = -G p It can be seen from Fig.28 that F a ( + 2) --- = -- = ----------------- = 1 + -G p 2 2 or a = -- + 1 p 2 a = -- - 1 2 p
Each of the eight possible values of alpha results in a different set of five values for the column voltages. Bias level F (see Fig.28) is half of the maximum row voltage level as shown by the equation V LCD F = -----------2 Figure 28 also shows that G is used to define the maximum column voltage level related to the VC level.
The BS[2:0] bias bits can be selected by a command and also can be programmed by OTP.
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Product specification
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The relationship between the parameters F, p, a and N (number of rows of the display) and the Von(rms) and Voff(rms) voltage values according to the typical LCD properties of the pixel are shown in equations (2) and (3). F p ( a + N + 2a ) V on(rms) = -- -----------------------------------------N a V off(rms) F p ( a + N - 2a ) = -- ----------------------------------------N a
2 2
OM6208
Table 14 Parameters of VLCD SYMBOL b a VALUE 0.03 3 CAUTION UNIT V V
(2)
(3)
11.10 LCD drive voltage 11.10.1 LCD DRIVE VOLTAGE GENERATION VLCD may be supplied externally or generated internally by the on-chip capacitive charge pump. OM6208 features on-chip capacitors resulting in a minimum of external components required for operation (see Chapter 16). The `power control' instruction may be used to switch VLCD generation on or off. The charge pump control instruction may be used to select the required voltage multiplication factor. The `set VPR' instruction is used for programming the LCD drive voltage VLCD. The generation of VLCD in OM6208 is illustrated in Fig.29. This shows all factors that effect VLCD generation, including the 6 bits of MMVOPCAL (from OTP) and the 7 bits resulting from the temperature compensation mechanism. Equations summarizing all factors are V OP = V PR + MMVOPCAL + V T (4) and V LCD = V OP b + a Where: VPR[7:0] is set in the instruction decoder and is the programmed VPR register value as an unsigned number MMVOPCAL[5:0] is the value of the offset stored in the OTP cells in twos complement format VT[7:0] in twos complement format comes from the temperature compensation block (see Table 16) a and b are fixed constant values (see Table 14). (5)
As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD (9 V), the user has to ensure, while setting the VPR register and selecting the temperature compensation, that under all conditions and including all tolerances VLCD remains below 9.0 V. Also, because the programming range for the internally generated VLCD allows values below the minimum allowed VLCD (5 V), the user has to ensure, while setting the VPR register and selecting the temperature compensation, that under all conditions and including all tolerances VLCD remains above 5.0 V.
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Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
handbook, full pagewidth
measured temperature slopes A B C D
VT TEMPERATURE TD MEASUREMENT 7 VT 8
-40
0
+85
T (C)
TEMPERATURE COMPENSATION MMVOPCAL [5:0] b a
VPR [7:0] 8 8 VOP
MGW833
VLCD
Fig.29 VLCD generation including the temperature compensation and OTP calibration.
handbook, full pagewidth
MGT847
V LCD
b
a
00
01
02
03
04
05
06
...
...
FD
FE
FF
V OP
VPR[7:0] programming: 00 to FF (HEX). Assuming MMVOPCAL = 0 and VT = 0 V.
Fig.30 VLCD programming of OM6208 shown as plots of equations (4) and (5).
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Product specification
65 x 96 pixels matrix grey-scale LCD driver
11.10.2 TEMPERATURE MEASUREMENT The temperature measurement is repeated every 10 seconds. The measured value is provided as a 7-bit digital value TD[6:0] which can be read back via the interface. The temperature can be determined from TD[6:0] using the equation T = ( 1.875 x TD - 40 )C (6) 11.10.3 TEMPERATURE COMPENSATION Due to the temperature dependency of the liquid crystal's viscosity, the LCD controlling voltage VLCD may have to be adjusted at different temperatures to maintain optimal contrast. Internal temperature compensation may be enabled via the `temperature compensation enable' instruction. When the internal temperature compensation is applied (TCE bit is set to 1) then according to Equation (4) the VLCD depends also on VT (the temperature compensation component defined in Table 16), otherwise VT is considered to be 0 V. After the reset, the VLCD is fixed because the VPR is a register that is reset to zero. The MMVOPCAL is also set to zero because this comes from the registers of OTP that are not refreshed yet, also VT is evaluated after the reset because the temperature measurement block supplies a TD value that is the default value stored in the register after the reset. The four temperature coefficients MA, MB, MC and MD correspond to four equally spaced temperature regions. Each coefficient can be selected from a choice of eight different slopes, or multiplication factors. Each one of these coefficients may be independently selected by the user via the `temperature compensation enable' instruction. The default for each slope register can be stored in OTP.
OM6208
Table 15 Temperature coefficients Slopes of VLCD are calculated from equations (4), (5), (6) and Table 16. SLA, SLB, SLC and SLD 111 110 101 100 011 010 001 000 MA, MB, MC and MD 3.00 2.00 1.25 1.00 0.75 0.50 0.25 0.00 SLOPE (mV/K) -48 -32 -20 -16 -12 -8 -4 0
Temperature compensation is implemented by adding an offset VT to the VPR value (additionally to the OTP calibration offset MMVOPCAL). The final result for VLCD calculation is an 8-bit positive number as shown in equations (4) and (5). Care must be taken by the user to ensure that the ranges of VPR, MMVOPCAL and VT do not cause clipping and hence undesired results. The adder stages will not permit overflow or underflow and will clamp results to either end of the range. The temperature read-out generates a 7-bit result, TD[6:0]. For temperatures below -40 C, the value of TD is zero. For temperatures above 79 C, the value of TD is higher than 63, but for VT calibration the value TD = 63 is used. The offset value VT may be calculated from Table 16. The effect on VLCD can be calculated by multiplying the offset value with the value of b (from Table 14). For example, if T = -10 C, TD = 16 and MB = 1.25 then VLCDoffset = 30 mV x (32 - 16) x 1.25 = 600 mV.
Table 16 Temperature compensation equations TEMPERATURE RANGE (C) -40 to -11 -10 to +19 +20 to +49 +50 to +79 TD RANGE 0 to 15 16 to 31 32 to 47 48 to 63 EQUATION VT = (16 x MB) + MA x (16 - TD) VT = (32 - TD) x MB VT = -(TD - 32) x MC VT = -(16 x MC) + MD x (TD - 48)
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
handbook, full pagewidth
A
B
C
D
MGW834
VLCD
-40
-10
20
50
80
T (C)
Fig.31 Example of segmented temperature coefficients.
11.11 Grey-scale mode and black-and-white mode It is possible to set via command the working mode of the OM6208. This is by setting the MOD bit of the `frame frequency' instruction, oscillator tune and mode. By default, the MOD bit is set to logic 0 and grey-scale mode is selected. In that mode, grey-scales are generated using Frame Rate Control (FRC). Three frames together form a super-frame. The frame frequency is adjustable but all three frames have the same duration. A grey-scale is generated by selecting either 0, 1, 2 or all 3 frames (see Table 17). If the MOD bit is set to logic 1 black-and-white mode is selected, meaning that only black-and-white levels are generated and only one frame type is sent to the display. Thus only the MSBs stored in the RAM are used for all three frames. The LSBs are ignored. Thus the way the data is stored in the RAM is the same as for grey-scale. As all frames are identical the frame frequency may be reduced (see Table 11).
Table 17 Grey-scale levels with FRC GS[1:0] SUPER-FRAME(1) GREY-SCALE LEVELS
Normal mode (E = 0) 0 0 1 1 0 1 0 1 000 001 110 111 white light grey dark grey black
Inverse mode (E = 1) 0 0 1 1 Note 1. The first and second frames in each super-frame are related to the MSB of GS[1:0] (GS = 11); the third frame is related to the LSB (GS = 00). 11.12 N-line inversion and frame inversion N-line inversion can be set from 0 to 127 as shown in Table 18. 0 1 0 1 111 110 001 000 black dark grey light grey white
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
Table 18 N-line inversion INVERSION AFTER 0-line inversion 1-line inversion 2-line inversion 3-line inversion 4-line inversion 5-line inversion 6-line inversion 7-line inversion 8-line inversion : 66-line inversion 67-line inversion 68-line inversion : 127-line inversion 0 only super-frame inversion 1-line inversion and super-frame inversion 2-line inversion and super-frame inversion 3-line inversion and super-frame inversion 4-line inversion and super-frame inversion 5-line inversion and super-frame inversion 6-line inversion and super-frame inversion 7-line inversion and super-frame inversion 8-line inversion and super-frame inversion : 66-line inversion and super-frame inversion 67-line inversion and super-frame inversion 68-line inversion and super-frame inversion : 127-line inversion and super-frame inversion Notes NL6 0 0 0 0 0 0 0 0 0 : 1 1 1 : 0 0 0 0 0 0 0 0 0 0 : 1 1 1 : 1 NL5 0 0 0 0 0 0 0 0 0 : 0 0 0 : 1 0 0 0 0 0 0 0 0 0 : 0 0 0 : 1 NL4 0 0 0 0 0 0 0 0 0 : 0 0 0 : 0 0 0 0 0 0 0 0 0 0 : 0 0 0 : 1 NL3 0 0 0 0 0 0 0 0 1 : 0 0 0 : 0 0 0 0 0 0 0 0 0 1 : 0 0 0 : 1 NL2 0 0 0 0 1 1 1 1 0 : 0 0 1 : 0 0 0 0 0 1 1 1 1 0 : 0 0 1 : 1 NL1 0 0 1 1 0 0 1 1 0 : 1 1 0 : 0 0 0 1 1 0 0 1 1 0 : 1 1 0 : 1
OM6208
NL0 0 1 0 1 0 1 0 1 0 : 0 1 0 : 0 0 1 0 1 0 1 0 1 0 : 0 1 0 : 1
FI 0 0 0 0 0 0 0 0 0 : 0 0 0 : 0 1 1 1 1 1 1 1 1 1 : 1 1 1 : 1
1. In grey-scale mode the super-frame inversion is performed if bit FI in the `N-line inversion and super-frame inversion' instruction is set to logic 1. In black-and-white mode, the super-frame inversion continues in groups of three frames. 2. NL[6:0] may be set in the range 0 to 127. If NL = 0, then no line inversion is performed; if NL = MUX rate = 68 then N-line inversion is equal to frame inversion. 3. With N-line inversion the output signal polarity changes every N row pulse periods (with p = 4 this means inversion occurs after every 4 x NL rows of the display). 4. If after a super-frame FI = 1 and there is an inversion due to an N-line inversion, this inversion occurs only once.
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This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... The example in Table 19 shows the first super-frame with the settings NL = 3, MUX = 20 and p = 4 applied; the super-frame contains three frames. The next super-frame will be a repeat of the first super-frame if bit FI is set to logic 0 (no super-frame inversion), or will start with the first frame having the opposite sign if bit FI is at logic 1 (super-frame inversion) and the N-line inversion counter will also restart. Super-frame inversion requires that the state of the previous super-frame is remembered, i.e., if the previous super-frame started `+', then the next super-frame must start `-'. This has priority over inversions triggered by the counter, so that if the counter triggers an inversion at a super-frame boundary and super-frame inversion is active, then the two do not cancel each other out but the super-frame inversion has priority. Table 19 Example showing line inversions in one super-frame: NL = 3, MUX = 20 and p = 4 SUPER-FRAME 1 FRAME 1 SUB FRAME 0 + + + + + 36 + + + + + + + - - - - - - - - SUB FRAME 1 - - - - + + + + + + + + + + + + - - - - SUB FRAME 2 - - - - - - - - + + + + + + + + + + + + SUB FRAME 3 - - - - - - - - - - - - + + + + + + + + SUB FRAME 0 + + + + - - - - - - - - - - - - + + + + FRAME 2 SUB FRAME 1 + + + + + + + + - - - - - - - - - - - - SUB FRAME 2 + + + + + + + + + + + + - - - - - - - - SUB FRAME 3 - - - - + + + + + + + + + + + + - - - - SUB FRAME 0 - - - - - - - - + + + + + + + + + + + + FRAME 3 SUB FRAME 1 - - - - - - - - - - - - + + + + + + + + SUB FRAME 2 + + + + - - - - - - - - - - - - + + + + SUB FRAME 3 + + + + + + + + - - - - - - - - - - - - Product specification 2003 feb 10 Philips Semiconductors
65 x 96 pixels matrix grey-scale LCD driver OM6208
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
12 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); notes 1 and 2. SYMBOL VDD1 VDD2, VDD3 VLCD VI ISS II, IO Ptot P/out Tstg Notes 1. Stresses above those listed under limiting values may cause permanent damage to the device. PARAMETER supply voltage (logic circuits) supply voltage (analog circuits) LCD supply voltage input voltage (any pad) ground supply current DC input or output current total power dissipation power dissipation per output storage temperature MIN. -0.5 -0.5 -0.5 -0.5 -50 -10 - - -65 MAX. +6.5 +5.0 +10.0 VDD1 + 0.5 +50 +10 300 30 +150
OM6208
UNIT V V V V mA mA mW mW C
2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 13 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS devices"). 14 DC CHARACTERISTICS VDD1 = 1.7 to 3.3 V; VSS = 0 V; VLCD = 5 to 9.0 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL VDD1 VDD2, VDD3 VLCDIN PARAMETER supply voltage (logic circuits) supply voltage (analog circuits) LCD supply voltage input LCD voltage supplied externally; high voltage generator disabled LCD voltage generated internally; high voltage generator enabled; note 1 with calibration; note 2 Power-down mode (all static currents switched off); note 3 notes 3 and 4 notes 3 and 4 DC load on VLCD = 300 A DC load on VLCD = 170 A IDD2 supply current; pin VDD2 notes 4 and 5 DC load on VLCD = 32 A 2003 feb 10 37 - 360 - A - - 2400 1200 - 2000 A A CONDITIONS MIN. 1.7 2.4 - - - - TYP. MAX. 3.3 4.5 9.0 UNIT V V V
VLCDOUT
LCD supply voltage output
-
-
9.0
V
VLCD(tol) IDD IDD1 IDD2, IDD3
tolerance of generated VLCD supply current; pins VDD1, VDD2 and VDD3 supply current; pin VDD1 supply current; pins VDD2 and VDD3
-70 - -
- 3 20
+70 - 40
mV A A
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
SYMBOL Logic circuits VOL VOH VIL VIH IL Rcol Rrow Vcol Vrow TRB Notes
PARAMETER
CONDITIONS
MIN. - - - - - 3 2 0 0 -
TYP.
MAX.
UNIT
LOW-level output voltage HIGH-level output voltage LOW-level input voltage HIGH-level input voltage leakage current
IOL = 0.5 mA IOH = -0.5 mA
VSS 0.8VDD1 VSS 0.7VDD1
0.2VDD1 VDD1 0.3VDD1 VDD1 +1
V V V V A k k mV mV C
VI = VDD1 or VSS VLCD = 7 V VLCD = 7 V; load 10 A; outputs tested one at a time
-1 - - -70 -70 -8
Column and row outputs column output resistance C0 to C95 row output resistance R0 to R64 bias tolerance C0 to C95 bias tolerance R0 to R64 7 5 +70 +70
Temperature read-back temperature read-back tolerance +8
1. The maximum possible VLCD voltage that may be generated is dependent on voltage, temperature and (display) load. 2. Valid for the values of temperature, VPR and temperature compensation used at calibration. 3. VDD1 = 1.8 V; VDD2 = 2.7 V; inputs at VDD1 or VSS; interface inactive; internal VLCD generation. 4. Grey-scale or black-and-white mode; display mode ON; all outputs open-circuit; BS[2:0] = 000. 5. VLCD = 6.84 V; default frequency; data pattern in RAM is with all bytes = AA(HEX); multiplication factor = 5.
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
15 AC CHARACTERISTICS VDD1 = 1.7 to 3.3 V; VSS = 0 V; VLCD = max. 9.0 V; Tamb = -40 to +85 C; all timings are between 20% and 80% of VDD1; unless otherwise specified. SYMBOL fOSC fEXT fframe fOSC, fframe PARAMETER oscillator frequency selection external clock frequency frame frequency selection accuracy of oscillator frequency and frame frequency default frequency: FR[2:0] = 001; T[2:0] = 110 VDD1 = 2.8 V; Tamb = -20 to +70 C CONDITIONS see Section 11.2, equation (1) MIN. 400(1) 400 35 -15 TYP. 496(2) 496 151.9 - MAX. 512(3) 512 210 +15 UNIT kHz kHz Hz %
Serial timing characteristics: 3-line and 4-line SPI and serial interface; VDD1 = 1.8 to 3.3 V; see Figs 32 to 35 fSCLK TCYC tPWH1 tPWL1 tS2 tH2 tPWH2 tS4 tH4 tS3 tH3 tS1 tH1 t1 t2 t3 t4 Cb Rb clock frequency SCLK clock cycle time SCLK pulse width high SCLK pulse width low SCE set-up time SCE hold time SCE minimum HIGH time SDATA set-up time SDATA hold time data/command set-up time data/command hold time SDATA set-up time SDATA hold time SDO access time SDO disable time SCE hold time SDO disable time capacitive load for SDO series resistance for SDO 3-line serial interface note 4 note 4 3-line SPI or 4-line SPI interface - 153 70 60 60 60 50 60 60 60 60 50 70 - - 50 25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 6.5 - - - - - - - - - - - - 50 50 - 110 50 500 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF
I2C-bus interface timing characteristics; VDD1 = 1.8 to 3.3 V; see Fig.36 fSCLH tSU;STA tHD;STA tLOW tHIGH tSU;DAT tHD;DAT trDA tfDA SCLH clock frequency set-up time (repeated) START condition hold time (repeated) START condition LOW period of the SCLH clock HIGH period of the SCLH clock data set-up time data hold time rise time of SDAH signal fall time of SDAH signal 0 160 160 160 60 10 15 20 20 3.4 - - - - - 70 80 80 MHz ns ns ns ns ns ns ns ns
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
SYMBOL tSU;STO Cb
PARAMETER set-up time for STOP condition capacitive load for SDAH and SCLH lines capacitive load for SDAH + SDA line and SCLH + SCL line note 5
CONDITIONS - - -
MIN. 160 - - - -
TYP.
MAX. - 100 400 5 -
UNIT ns pF pF ns V
tSW VnL
tolerable spike width on bus noise margin at the LOW level for each connected device (including hysteresis) noise margin at the HIGH level for each connected device (including hysteresis)
0.1VDD -
VnH
0.2VDD -
-
V
RESET timing characteristics; see Fig.37 tVHRL tRW tRWS Notes 1. fOSC defined for T[2:0] = 000. 2. fOSC defined for T[2:0] = 110 (default value). 3. fOSC defined for T[2:0] = 111. 4. Maximum value is for fSCLK = 6.5 MHz; series resistance includes ITO track + connector resistance + PCB. 5. Cb = 100 pF total capacitance of one bus line. 6. RES may be LOW before VDD1 goes HIGH. VDD to RES LOW reset low pulse width reset pulse width spike suppression 0(6) 1000 - - - - 1 - 100 s ns ns
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
handbook, full pagewidth
t S2
t H2
t PWH2
SCE t S2 t PWL1 SCLK t PWH1 T cyc
t S1 SDATA
t H1
MGU642
Fig.32 3-line serial interface timing.
handbook, full pagewidth
t S2
t H2
t PWH2
SCE t S3 D/C t S2 t PWL1 SCLK t PWH1 T cyc t H3
t S4 SDATA
t H4
MGU643
Fig.33 4-line SPI interface timing.
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
handbook, full pagewidth
SCE t3 SCLK t H1 SDATA t S1
t1 SDO
t2
MCE174
Fig.34 3-line and 4-line SPI timing (read mode).
handbook, full pagewidth
SCE t3 SCLK t H1 SDATA t S1
t1 SDO
t4
MCE175
Fig.35 3-line serial interface timing (read mode).
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
handbook, full pagewidth
Sr tfDA
trDA
Sr
P
SDAH
tSU;STA
tHD;DAT tHD;STA tSU;DAT
tSU;STO
SCLH tfCL trCL1
(1)
trCL tHIGH tLOW tLOW tHIGH
trCL1
(1)
MGK871
= MCS current source pull-up = Rp resistor pull-up
Fig.36 I2C-bus timing diagram (Hs-mode).
handbook, full pagewidth
VDD1 t RW RES t RW t RWS
VDD1 t VHRL t RW t RW
RES
MGW835
Fig.37 Reset timing.
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
16 APPLICATION INFORMATION 16.1 Protection from light 16.3 Application examples
OM6208
Semiconductors are light sensitive. Exposure to light sources can cause malfunction of the IC. In the application it is therefore required to protect the IC from light. The protection has to be done on all sides of the IC, i.e. front, rear and all edges. 16.2 Chip-on-glass displays
In the following application examples, the required values of the external capacitors are: * CVLCD = 1 F minimum * CVDD, CVDD1 and CVDD2 = 1 F minimum * Higher capacitor values can be used for the supply. When the internal charge pump is used, the VLCD lines must be short-circuited externally to ensure that the resistance between pads is zero. This is to allow the bias system to work correctly when BS[2:0] is not 000.
The pinning of the OM6208 has an optimal design for single plane wiring, e.g. for chip-on-glass display modules.
handbook, full pagewidth
DISPLAY 65 x 96 pixels
32
96
33
OM6208
VDD2,3 VDD1 VSS1 VSS2 CVDD VDD VSS
CVLCD I/O
MGW836
Fig.38 Application example using the internal charge pump and a single VDD source.
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VLCDSENSE VLCDOUT VLCDIN
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
handbook, full pagewidth
DISPLAY 65 x 96 pixels
32
96
33
OM6208
VDD2,3 VDD1 VSS1 VSS2 CVDD2 VDD2 VSS
C VDD1 VDD1 I/O
CVLCD
MGW837
Fig.39 Application example using the internal charge pump and two separate VDD sources (VDD1 and VDD2).
handbook, full pagewidth
DISPLAY 65 x 96 pixels
32
96
VLCDSENSE VLCDOUT VLCDIN
33
OM6208
VDD2 VDD1 VSS1 VSS2
CVDD VDD VSS
I/O
VLCDSENSE VLCDOUT VLCDIN
VLCDIN
MGW838
Fig.40 Application example using external high voltage generation.
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
17 MODULE MAKER PROGRAMMING One Time Programmable (OTP) technology has been implemented in the OM6208. This enables the module maker to program some extended features of the OM6208 after it has been assembled on an LCD module. Programming is made under the control of the interfaces and the use of one special pin. This pin must be made available on the module glass but does not need to be accessed by the set maker. The OM6208 features the following module maker programmable parameters: * VLCD calibration * Default temperature compensation slopes * Default charge pump multiplication factor * Default VPR value * Default bias levels BS[2:0] * Default frame frequency range in grey-scale mode GFR[2:0] * Default oscillator tuning in grey-scale mode GT[2:0] * Default frame frequency in black-and-white mode SFR[2:0] * Default oscillator tune in black-and-white mode ST[2:0] * Default N-line inversion NL[6:0] * Default frame inversion FI * Enable factory default FD * Seal bit. 5 0 0 0 : 0 0 0 1 1 : 1 1 1 17.1 VLCD calibration
OM6208
The first OTP feature included is the ability to tune the VLCD voltage with a 6-bit code (MMVOPCAL). This code is implemented in twos complement notation giving rise to a positive or negative offset to the VPR register. The adder in the circuit has underflow and overflow protection. In the event of an overflow, the output will be clamped to 255; with an underflow, the output will be clamped to logic 0. The final control to the high voltage generator, VOP, will be the sum of all the calibration registers according to Section 11.10, equation (4). Table 20 VLCD calibration MMVOPCAL 4 1 1 1 : 0 0 0 1 1 : 0 0 0 3 1 1 1 : 0 0 0 1 1 : 0 0 0 2 1 1 1 : 0 0 0 1 1 : 0 0 0 1 1 1 0 : 1 0 0 1 1 : 1 0 0 DECIMAL EQUIVALENT 0 1 0 1 : 0 1 0 1 0 : 0 1 0 31 30 29 : 2 1 0 -1 -2 : -30 -31 -32 VLCD OFFSET (mV) 930 900 870 : 60 30 0 -30 -60 : -900 -930 -960
handbook, full pagewidth
Temperature compensation VT, 7 bit value
range: - 64 to + 63
VT [6:0] range: -32 to + 31
OTP VLCD calibration, 6 bit offset MMVOPCAL [5:0]
+
range: 0 to + 255 (usable range + 32 to + 224)
VOP range: 0 to + 255
to high voltage generator
VPR register, 8 bit value VPR [7:0]
MGW839
Fig.41 VLCD calibration.
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
17.2 17.2.1 Factory defaults CONFIGURATION DERIVED FROM OTP CELLS * Default N-line inversion NL[6:0] * Default frame inversion FI * Enable factory default FD * Seal bit.
OM6208
In some instances it is desirable that the configuration is derived from OTP cells and not from user-configurable registers. It is therefore possible to pre-define the following features using the OTP facility: * Default temperature compensation slopes * Default charge pump multiplication factor * Default VPR value * Default bias levels BS[2:0] * Default frame frequency range in grey-scale mode GFR[2:0] * Default oscillator tune in grey-scale mode GT[2:0] * Default frame frequency in black-and-white mode SFR[2:0] * Default oscillator tune in black-and-white mode ST[2:0]
The selection of the mode for factory defaults is made by setting the factory default OTP cell bit MMFD. Table 21 Factory default bit MMFD MMFD 0 1 ACTION configuration data is taken from the interface OTP values are used for configuration data
The operation can be shown as a switch that selects between two sources of data (see Fig.42). When the OTP defaults are selected, changing the default values via the interface is not possible.
handbook, full pagewidth
FACTORY DEFAULT MMFD =0 to temperature compensation circuit
INTERFACE
INTERFACE REGISTERS e.g. SLA [2:0]
OTP DEFAULTS e.g. SLA [2:0]
MMFD =1
MGW840
Fig.42 Factory defaults.
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
17.2.2 DEFAULTS FROM INTERFACE REGISTERS
OM6208
Factory defaults available from user-configurable registers are as follows: * Temperature slope selection values are set by SLA[2:0], SLB[2:0], SLC[2:0] and SLD[2:0] * Default charge pump multiplication factor value is set by S[1:0] * Default VPR value is set by VPR[7:0] * Default bias level values are set by BS[2:0] * Grey-scale mode default frame frequency and tuning values are set by GFR[2:0] and GT[2:0] * Black-and-white mode default frame frequency and tuning values are set by SFR[2:0] and ST[2:0]. 17.3 Seal bit
calibration mode. This seal bit, once programmed, cannot be reversed, thus further changes in programmed values are not possible. Applying the programming voltages when not in CALMM mode has no effect on the programmed values. Table 22 Seal bit definition SEAL BIT 0 1 17.4 ACTION possible to enter calibration mode calibration mode disabled
OTP architecture
The module maker programming is performed in a special mode: the calibration mode (CALMM). This mode is entered via a special interface command, CALMM. To prevent wrongful programming, a seal bit has been implemented which prevents the device from entering the
The OTP circuitry in the OM6208 contains many bits of data. The circuitry for one bit is called an OTP slice. Each OTP slice consists of two main parts: the OTP cell (a non-volatile memory cell) and the shift register cell (a flip-flop). The OTP cells are accessible only through their shift register cells: both reading from and writing to the OTP cells are performed with the shift register cells, but only the shift register cells are visible to the rest of the circuit. The basic OTP architecture is shown in Fig.43.
handbook, full pagewidth
DATA TO THE CIRCUIT FOR CONFIGURATION AND CALIBRATION OTP slice SHIFT REGISTER DATA INPUT
SHIFT REGISTER FLIP-FLOP
SHIFT REGISTER
read data from the OTP cell
write data to the OTP cell
OTP CELLS
MGW841
OTP CELL
Fig.43 Basic OTP architecture.
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
17.4.1 OTP OPERATIONAL EFFECTS
OM6208
The OTP architecture allows the following operations: * Reading data from the OTP cells. The content of the non-volatile OTP cells is transferred to the shift register where upon it may affect the OM6208 operation. * Writing data to the OTP cells. First, all 9 bits of data are shifted into the shift register via the interface. Then the content of the shift register is transferred to the OTP cells (there are some limitations related to storing data in these cells, see Section 17.7). * Checking calibration without writing to the OTP cells. Shifting data into the shift register allows the effects on the VLCD voltage to be observed. The reading of data from the OTP cells is initiated by writing to the DON register. The OTP cells will not be updated until the device leaves power down and the oscillator starts. The reading operation needs up to 5 ms to complete.
The shifting of the data into the shift register is performed in the special mode CALMM. In the OM6208, the CALMM mode is entered through the CALMM command. Once in the CALMM mode the data is shifted into the shift register via the interface at the rate of 1-bit per command. After transmitting the last bit and exiting the CALMM mode the serial interface is again in the normal mode and all other commands can be sent. Care should be taken that always all bits of data (or a multiple of all bits) are transferred before exiting the CALMM mode, otherwise the bits will be in the wrong positions. In the shift register the value of the seal bit is, like the other bits, always zero at reset. To make sure the security feature works correctly, the CALMM command is disabled until a Power-down mode has been left. Once a refresh is completed, the seal bit value in the shift register is valid and permission to enter CALMM mode can thus be determined. The bits are shifted into the shift register in a predefined order as shown in Table 23.
Table 23 OTP bit order (See Fig.44 for a graphical representation) POSITION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 OTP CELL MMVPR[7] MMVPR[6] MMVPR[5] MMVPR[4] MMVPR[3] MMVPR[2] MMVPR[1] MMVPR[0] MMSLD[2] MMSLD[1] MMSLD[0] MMSLC[2] MMSLC[1] MMSLC[0] MMSLB[2] MMSLB[1] MMSLB[0] MMSLA[2] POSITION 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 OTP CELL MMSLA[1] MMSLA[0] MMS[1] MMS[0] MMBS[2] MMBS[1] MMBS[0] MMFD MMVOPCAL[5] MMVOPCAL[4] MMVOPCAL[3] MMVOPCAL[2] MMVOPCAL[1] MMVOPCAL[0] MMGFR[2] MMGFR[1] MMGFR[0] MMGT[2] POSITION 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 - OTP CELL MMGT[1] MMGT[0] MMSFR[2] MMSFR[1] MMSFR[0] MMST[2] MMST[1] MMST[0] MMNL[6] MMNL[5] MMNL[4] MMNL[3] MMNL[2] MMNL[1] MMNL[0] MMFI SEAL -
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Product specification
65 x 96 pixels matrix grey-scale LCD driver
17.5 Interface commands
OM6208
Table 24 OTP instructions These instructions are in addition to those in the Instruction set, Table 7. COMMAND BYTE NAME OTP programming DON (refresh) Load 0 Load 1 D/C D7 0 1 D6 1 D5 1 D4 1 D3 0 D2 0 D1 OSE D0 CALMM enter calibration mode and control programming DON 0 1 display ON/OFF write 0 to shift register write 1 to shift register ACTION
0 0 0
1 1 1
0 1 1
1 0 0
0 1 1
1 1 1
1 0 0
1 0 0
17.5.1
CALMM INSTRUCTION
17.5.2
REFRESH INSTRUCTION
This instruction enters the device into the calibration mode. This mode enables the shift register for loading and allows programming of the non-volatile OTP cells to take place. If the seal bit is set, then this mode cannot be accessed and the instruction will be ignored. Once in calibration mode, data may be loaded into the shift register via the `LOAD0' and `LOAD1' instructions (on the falling edge of SCLK). The CALMM mode may be left by setting the CALMM bit to logic 0. Reset will also clear this mode. The programming can only take place when OTP Switch Enable (OSE) has been set to logic 1. This bit enables the VOTPPROG input to be passed to the OTP cells. This allows VOTPGATE to be tied to SCLH/SCE on the module for normal operation. Reset will also clear this mode.
The action of the `refresh' instruction is to force the OTP shift register to reload from the non-volatile OTP cells. This instruction takes up to 5 ms to complete. During this time all other instructions may be sent. In the OM6208 the `refresh' instruction is associated with the `DON' instruction so that the shift register is automatically refreshed every time DON is enabled or disabled. Note: If this instruction is sent while in power save mode, the DON bit will be updated but the refreshing is delayed until the device leaves power-down.
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
17.6 Example of filling the shift register
OM6208
An example sequence of commands and data is shown in Table 25. In this example the shift register is filled with the following data: MMVPR = 11010000, and the seal bit is logic 0. It is assumed that the OM6208 has just been reset. After transmitting the last bit, the OM6208 can exit or remain in CALMM mode (see step 1). Note that while in CALMM Table 25 Example sequence for filling the shift register STEP 1 2 3 4 5 6 7 8 9 10 : 57 58 59 Note : 0 0 0 : 1 1 1 : 1 1 1 : 0 0 1 : 1 1 1 : 1 1 0 : 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 D/C 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1
mode the interface does not recognize commands in the normal sense. After this sequence has been applied it is possible to observe the impact of the data shifted in. The sequence described is not useful for OTP programming because the number of bits with the value logic 1' is greater than that allowed for programming (see Section 17.7). The shift register contents after this action are shown in Fig.44.
D1 1 0 0 0 0 0 0 0 : 0 0 0
D0 1 1 1 1 0 1 0 0 : 1 0 0 MMFI seal bit
ACTION exit power-down wait 5 ms for refresh to take effect enter CALMM mode shift in data, first bit is MMVPR[7]; note 1 MMVPR[6] MMVPR[5] MMVPR[4] MMVPR[3] MMVPR[2]
exit CALMM mode
1. The data for the bits is not in the correct shift register position until all bits have been sent.
handbook, full pagewidth
OTP SHIFT REGISTER SEAL BIT MMFI LSB 0 1 0 0 MMNL [6:0] 0 1 1 1
MSB
shifting direction
MMST MMSLD [2:0] 1 1 0 1
LSB
MMVPR [7:0] 0 0 0 1 0 1
MSB
0
0
1
MGW842
Fig.44 Shift register contents after example sequence of Table 25.
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
17.7 Programming flow
OM6208
Programming is achieved whilst in CALMM mode and with the application of the programming voltages. As the data for programming the OTP cell is contained in the corresponding shift register cell, the shift register cell must be loaded with a logic 1 in order to program the corresponding OTP cell. If the shift register cell contains a logic 0, then no action will take place when the programming voltages are applied. Once an OTP cell is programmed it cannot be de-programmed. An already programmed cell (an OTP cell containing a logic 1) must not be reprogrammed. A sequence of commands and data for OTP programming is shown as an example in Table 26. Table 26 Sequence for OTP programming This sequence assumes the OM6208 has just been reset. STEP 1 2 3 4 5 6 7 7 9 10 : 58 59 60 : 0 0 : 1 1 : 1 1 : 0 0 : 1 1 : 1 1 : 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 D/C 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1
Although the order for programming cells is not significant, it is recommended that the seal bit is programmed last. Once this bit has been programmed it will not be possible to re-enter the CALMM mode. During programming, a substantial current flows in the VLCDIN pin. For this reason it is recommended programming only one OTP cell at a time. This is achieved by filling all but one shift register cells with logic 0. The programming specification refers to the voltages at the chip pads, therefore the contact resistance is significant and must be considered by the user.
D1 1 1 0 0 0 0 0 0 : 0 1
D0 1 1 1 0 0 0 0 0 : 0 0 MMFI seal bit
ACTION exit power-down (DON = 1) wait 5 ms for refresh to take effect enter CALMM mode and OSE shift-in data, MMVPR[7] is first bit; note 1 MMVPR[6] MMVPR[5] MMVPR[4] MMVPR[3] MMVPR[2]
apply programming voltage at pins VOTPPROG and VLCDIN according to Section 17.8 Repeat steps 5 to 60 for each bit that should be programmed to 1 apply external reset
61 Note
1. The data for the bits is not in the correct shift register position until all the bits have been sent.
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
17.8 Programming specification
OM6208
Table 27 Programming specification (refer to Fig.45) SYMBOL VOTPPROG PARAMETER voltage applied to pad VOTPPROG CONDITION VOTPPROG relative to VSS1; note 1 programming active programming inactive VLCDIN voltage applied to pad VLCDIN VLCDIN relative to VSS1; notes 1 and 2 programming active programming inactive ILCDIN IOTPPROG current drawn by pad VLCDIN during programming current drawn by pad VOTPPROG during programming ambient temperature during programming internal data set-up time after last clock internal data hold time before next clock VOTPPROG gate set-up time prior to programming VOTPPROG gate hold time after programming pulse width of programming voltage when programming a single bit to logic 1 9.0 VSS2 - - 9.5 VDD2 850 100 10.0 4.5 1000 200 V V A A 11.0 11.5 12.0 VDD1 V V VSS - 0.2 0 MIN. TYP. MAX. UNIT
TPROG tsu(SCLK) thd(SCLK) tsu(gate) thd(gate) tPW Notes
0 1 1 1 1 100
25 - - - - 120
40 - - 10 10 200
C s s s s ms
1. The voltage drop across the ITO track and zebra connector must be taken into account to guarantee sufficient voltage at the chip pads. 2. The Power-down mode (DON = 0 and DAL = 1) and CALMM mode must be active while the VLCDIN input is being driven.
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
handbook, full pagewidth
t su(SCLK)
t hd(SCLK)
SCLK
VVOTPPROG
VLCDIN
t su(gate) t PW
t hd(gate)
MGW843
Fig.45 Programming waveforms.
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Product specification
65 x 96 pixels matrix grey-scale LCD driver
18 DEVICE PROTECTION DIAGRAM
OM6208
handbook, full pagewidth
VDD1
VDD2
VDD3
VSS1
VSS1 VSS2
VSS1
VSS2
VLCDIN , VLCDSENSE
VLCDOUT
VSS1 VSS1
VSS1
VOTPPROG
VLCDIN
VDD1 SCLK, SDATA, SDO
VSS1
LCD outputs
VSS1
VSS1
VDD1 OSC, RES, D/C, PS [2:0], T1, T2, T5 VSS1 I2C-bus pads
VDD1
VDD1
T3, T4, VSS1, VDD VSS1
VSS1
MGW850
Protection diode maximum forward current = 5 mA.
Fig.46 Protection circuit diagrams.
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Product specification
65 x 96 pixels matrix grey-scale LCD driver
19 BONDING PAD INFORMATION
OM6208
handbook, full pagewidth
R32 RES VOTPPROG SCLH/SCE ID3/SA0, ID4/SA1 C95 MX VSS1, VSS2 SDATA SDO SDAH SCLK SDAHOUT VDD1 C0 PS [1:0] D/C OSC VDD2, VDD3 VLCDIN, VLCDOUT, VLCDSENSE
MGW844
33 row driver outputs R64
x y
96 column driver outputs
R31
32 row driver outputs
R0
Fig.47 Bonding pad locations (viewed from bump side).
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
Table 28 Bonding pad locations All x and y coordinates indicate pad centres and are referenced to the centre of the chip; dimensions in m (see Fig.47). COORDINATES SYMBOL dummy dummy alignment mark dummy VLCDIN VLCDIN VLCDIN VLCDIN VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDSEN VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD3 VDD3 VDD3 OSC DC PS1 PS0 VDD1 VDD1 VDD1 2003 feb 10 PAD x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 -4919 -4856 -4762 -4649 -4586 -4523 -4460 -4397 -4323 -4260 -4197 -4134 -4071 -4008 -3945 -3882 -3566 -3503 -3440 -3377 -3314 -3251 -3188 -3125 -3062 -2999 -2928 -2865 -2802 -2639 -2475 -2345 -2217 -2102 -2039 -1976 y +1279 +1279 +1220 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 57
OM6208
COORDINATES SYMBOL VDD1 VDD1 VDD1 dummy dummy dummy dummy SDAHOUT dummy SCLK dummy dummy dummy dummy dummy SDAH SDO SDATA VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 MX T3 T4 T1 T2 T5 T6 ID3_SA0 PAD x 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 -1913 -1850 -1787 -1669 -1503 -1337 -1172 -1006 -829 -657 -468 -303 -137 29 194 360 605 696 795 858 921 984 1047 1110 1173 1246 1309 1372 1435 1498 1561 1693 1865 2028 2114 2232 2350 2468 2586 y +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 +1279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
COORDINATES SYMBOL ID4_SA1 VDD1 dummy dummy dummy dummy dummy SCLH VOTPPROG VOTPPROG VOTPPROG dummy RES dummy dummy dummy dummy alignment mark bumps alignment mark dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 2003 feb 10 PAD x 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 2704 2849 3005 3171 3336 3502 3667 3833 3958 4021 4084 4243 4387 4489 4552 4615 4678 4799 4902 +4900 +4849 +4797 +4745 +4693 +4641 +4589 +4538 +4486 +4434 +4330 +4278 +4227 +4175 +4123 +4071 +4019 +3967 +3916 +3864 y 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1 279 1220 1258 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 58 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 VC dummy dummy T8 T7 V1_L C95 C94 C93 C92 C91 C90 C89 C88 C87 C86 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 SYMBOL PAD
COORDINATES x +3812 +3760 +3708 +3656 +3604 +3553 +3501 +3449 +3397 +3345 +3293 +3242 +3190 +3138 +3086 +3034. +2982 +2931 +2879 +2829 +2775 +2723 +2671 +2620 +2568 +2516 +2413 +2360 +2308 +2257 +2205 +2153 +2101 +2049 +1997 +1946 +1894 +1842 +1790 y -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
COORDINATES SYMBOL C85 C84 C83 C82 C81 C80 C79 C78 C77 C76 C75 C74 C73 C72 C71 C70 C69 C68 C67 C66 C65 C64 C63 C62 C61 C60 C59 C58 C57 C56 C55 C54 C53 C52 C51 C50 C49 C48 dummy PAD x 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 +1738 +1686 +1635 +1583 +1531 +1479 +1427 +1375 +1324 +1272 +1219.86 +1168 +1116 +1064 +961 +909 +857 +805 +753 +701 +650 +598 +546 +494 +442 +390 +339 +287 +235 +183 +131 +79 +28 -24 -76 -128 -180 -232 -283 y -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 dummy C47 C46 C45 C44 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 SYMBOL PAD
COORDINATES x -335 -387 -439 -491 -543 -595 -646 -698 -750 -802 -854 -906 -957 -1 009 -1061 -1113 -1165 -1217 -1268 -1320 -1372 -1424 -1476 -1528 -1579 -1683 -1735 -1787 -1839 -1891 -1942 -1994 -2046 -2098 -2150 -2202 -2253 -2305 -2357 y -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
COORDINATES SYMBOL C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 dummy dummy V1_H V2_L V2_H R31 R30 R29 R28 R27 R26 R25 R24 R23 R22 PAD x 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 -2409 -2461 -2513 -2564 -2616 -2668 -2720 -2772 -2824 -2875 -2927 -2979 -3031 -3083 -3135 -3187 -3238 -3290 -3342 -3394 -3446 -3498 -3549 -3601 -3653 y -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 R21 R20 R19 R18 R17 R16 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 dummy dummy 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 SYMBOL PAD
COORDINATES x -3705 -3757 -3809 -3860 -3912 -3964 -4016 -4068 -4120 -4171 -4223 -4275 -4327 -4379 -4431 -4483 -4534 -4586 -4638 -4690 -4742 -4794 -4845 -4897 y -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275 -1275
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
Table 29 Chip information ITEM Row/column side Pad pitch CBB opening Bump dimensions Bump height Minimum bump distance Wafer thickness (excl. bumps) Interface side Pad pitch CBB opening Bump dimensions Bump height Minimum bump distance Wafer thickness (excl. bumps) 63 (minimum) 25.7 x 5.4 42 x 90 (3) 15.0 shortened bumps: 21 normal bumps: 22 381 (25) m m m m m m
x
OM6208
ROW/COL SIDE
UNIT m m m m m m
y bump distance
handbook, halfpage
51.84 (minimum) 15.3 x 5.4 30.0 x 99 (3) 15.0 21.8 381 (25)
10.140 mm
2.840 mm
OM6208
pitch
MGW845
Fig.48 Chip size and pad pitch.
handbook, halfpage
handbook, halfpage
60 m
y centre
90 m
y centre
60 m
x centre
MGW846
x centre
MGW847
Fig.49 Shape of alignment mark.
Fig.50 Shape of bump alignment mark.
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Product specification
65 x 96 pixels matrix grey-scale LCD driver
20 TRAY INFORMATION
OM6208
handbook, full pagewidth
x
A
C
y
D
B F
E
MGW848
Fig.51 Tray details.
Table 30 Tray dimensions DIM.
handbook, halfpage
DESCRIPTION pocket pitch, x direction pocket pitch, y direction pocket width, x direction pocket width, y direction tray width, x direction tray width, y direction number of pockets in X direction number of pockets in Y direction
VALUE 14.25 mm 4.87 mm 10.24 mm 2.94mm 50.80 mm 50.80 mm 3 9
A B C
OM6208-1
D E F x
MGW849
y
The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram (Fig.47) for the orientation and position of the type name on the die surface.
Fig.52 Tray alignment.
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Product specification
65 x 96 pixels matrix grey-scale LCD driver
21 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
OM6208
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 22 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 23 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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Product specification
65 x 96 pixels matrix grey-scale LCD driver
Bare die All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips Semiconductors has no control of third party procedures in the sawing, handling, 24 PURCHASE OF PHILIPS I2C COMPONENTS
OM6208
packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used.
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Product specification
65 x 96 pixels matrix grey-scale LCD driver
NOTES
OM6208
2003 feb 10
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
NOTES
OM6208
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
NOTES
OM6208
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403512/02/pp68
Date of release: 2003
feb 10
Document order number:
9397 750 11077

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